Redmi Note 10 Pro startup modem analysis

Redmi Note 10 Pro
Dimensity 1100
CPU model is MT6891Z/CZA
(MT6885, Dimensity 1000L, MediaTek’s first 5G chip)

/sys/kernel/ccci
/sys/class/ccci_node/ccci_ccb_meta
/sys/class/ccci_node/ccci_ccb_md_monitor
/sys/class/ccci_node/ccci_raw_mdm
/sys/class/ccci_node/ccci_mdl_monitor

/sys/class/ccci_md_sta/ccci_md1_sta
/sys/firmware/devicetree/base/mddriver/ccci,modem_info_v2

drivers/misc/mediatek/ccci_util/ccci_util_lib_load_img.c

drivers/misc/mediatek/ccci_util/ccci_util_lib_sys.c


drivers/misc/mediatek/eccci/ccci_core.c
    ccci_init(void)



drivers/misc/mediatek/eccci/mt6885/ccci_platform.c
     ccci_plat_common_init


Configure address

drivers/misc/mediatek/eccci/ccci_modem.c
void ccci_md_config(struct ccci_modem *md)
{
	phys_addr_t md_resv_mem_addr = 0,
		md_resv_smem_addr = 0, md1_md3_smem_phy = 0;
	unsigned int md_resv_mem_size = 0,
		md_resv_smem_size = 0, md1_md3_smem_size = 0;
	int amms_pos_size = 0;
	phys_addr_t bank4_phy_addr;
...
...
	/* Get memory info */
	get_md_resv_mem_info(md->index, &md_resv_mem_addr,
		&md_resv_mem_size, &md_resv_smem_addr, &md_resv_smem_size);
	get_md1_md3_resv_smem_info(md->index, &md1_md3_smem_phy,
		&md1_md3_smem_size);
	/* setup memory layout */
	/* MD image */
	md->mem_layout.md_bank0.base_ap_view_phy = md_resv_mem_addr;
	md->mem_layout.md_bank0.size = md_resv_mem_size;
	/* do not remap whole region, consume too much vmalloc space */
	md->mem_layout.md_bank0.base_ap_view_vir =
		ccci_map_phy_addr(
			md->mem_layout.md_bank0.base_ap_view_phy,
			MD_IMG_DUMP_SIZE);
	/* Share memory */
	/*
	 * MD bank4 is remap to nearest 32M aligned address
	 * assume share memoy layout is:
	 * |---AP/MD1--| <--MD1 bank4 0x0 (non-cacheable)
	 * |--MD1/MD3--| <--MD3 bank4 0x0 (non-cacheable)
	 * |---AP/MD3--|
	 * |--non-used_-|
	 * |--cacheable--| <-- MD1 bank4 0x8000000 (for 6292)
	 * this should align with LK's remap setting
	 */



eccci/modem_sys1.c
    ccci_set_mem_access_protection_1st_stage(md);


eccci/fsm/ccci_fsm.c

    ccci_set_mem_access_protection_second_stage

#define IMG_MAGIC 0x58881688
#define EXT_MAGIC 0x58891689

#define IMG_NAME_SIZE 32
#define IMG_HDR_SIZE 512
union prt_img_hdr {
	struct {
		/* always IMG_MAGIC */
		unsigned int magic;
		/* image size, image header and padding are not included */
		unsigned int dsize;
		char name[IMG_NAME_SIZE];
		/* image load address in RAM */
		unsigned int maddr;
		/* maddr is counted from the beginning or end of RAM */
		unsigned int mode;
		/* extension */
		/* always EXT_MAGIC */
		unsigned int ext_magic;
		/* header size is 512 bytes currently,
		 * but may extend in the future
		 */
		unsigned int hdr_size;
		/* see HDR_VERSION */
		unsigned int hdr_version;
		/* please refer to #define beginning with SEC_IMG_TYPE_ */
		unsigned int img_type;
		/* end of image list?
		 * 0: this image is followed by another image
		 * 1: end
		 */
		unsigned int img_list_end;
		/* image size alignment setting in bytes,
		 * 16 by default for AES encryption
		 */
		unsigned int align_size;
		/* high word of image size for 64 bit address support */
		unsigned int dsize_extend;
		/* high word of image load address in RAM
		 * for 64 bit address support
		 */
		unsigned int maddr_extend;
	} info;
	unsigned char data[IMG_HDR_SIZE];
};